{"title":"四阶串并联加法器的设计","authors":"A. Das, I. Jahangir, M. Hasan","doi":"10.1109/ICELCE.2010.5700730","DOIUrl":null,"url":null,"abstract":"Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the gate delays of full adder and logarithmic stage parallel using mathematical expressions.","PeriodicalId":202650,"journal":{"name":"International Conference on Electrical & Computer Engineering (ICECE 2010)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Design of quaternary serial and parallel adders\",\"authors\":\"A. Das, I. Jahangir, M. Hasan\",\"doi\":\"10.1109/ICELCE.2010.5700730\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the gate delays of full adder and logarithmic stage parallel using mathematical expressions.\",\"PeriodicalId\":202650,\"journal\":{\"name\":\"International Conference on Electrical & Computer Engineering (ICECE 2010)\",\"volume\":\"231 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Electrical & Computer Engineering (ICECE 2010)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICELCE.2010.5700730\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Electrical & Computer Engineering (ICECE 2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICELCE.2010.5700730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the gate delays of full adder and logarithmic stage parallel using mathematical expressions.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
