时间冗余纠错加法器和乘法器

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI:10.1109/DFTVS.1992.224350

Y. Hsu, E. Swartzlander

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引用次数: 41

摘要

时间冗余是在不引入太多硬件开销的情况下实现容错的一种方法，可用于时间不重要的应用程序。将Johnson提出的基于重复比较的重计算检错加法器扩展为纠错加法器。本文还提出了一种可以检测和校正误差的时间冗余乘法器。时间冗余纠错加法器和乘法器的硬件开销比硬件或信息冗余方法要低得多。因此，它们在主要考虑硬件复杂性的系统中非常有用。

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Time redundant error correcting adders and multipliers

Time redundancy is an approach to achieve fault-tolerance without introducing too much hardware overhead and can be used in applications where time is not critical. The basic REcomputing with Duplication With Comparison error-detecting adder proposed by Johnson is extended to perform error correction. Time redundant multipliers that can detect and correct errors are also proposed in this paper. The hardware overhead of time redundant error correcting adders and multipliers is much lower than that of hardware or information redundancy approaches. Hence they are useful in systems where hardware complexity is the primary concern.<>

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Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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