一个并行累加有符号数组的技巧

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2017-10-01 DOI:10.1109/EDSSC.2017.8126440

Jinnan Ding, Shuguo Li

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引用次数: 1

摘要

大数加法是密码学算法中的基本运算。本文通过引入非最小正形式，加速了硬件设计中的大加法运算，有利于并行处理。用该方法实现的256位有符号阵列累加器，速度比传统设计提高18%，面积延迟比传统设计提高15%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A trick for parallel accumulation of signed array

Large number addition is the fundamental operation in cryptography algorithms. In this paper, we accelerate large addition in hardware design by introducing non-least-positive form, which is beneficial to parallel processing. An implementation of 256-bit signed array accumulator with our method shows an improvement of 18% in speed and 15% in area-delay product compared with traditional design.

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2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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