故障覆盖率100%的ATG阵列架构

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI:10.1109/DFTVS.1991.199966

K. El-Ayat, R. Cahn, C. L. Chan, T. Speers

{"title":"故障覆盖率100%的ATG阵列架构","authors":"K. El-Ayat, R. Cahn, C. L. Chan, T. Speers","doi":"10.1109/DFTVS.1991.199966","DOIUrl":null,"url":null,"abstract":"Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design implemented in the array circuit. In addition to architecture and circuit implementation details, the paper discusses the ATG generation methodology and algorithms, circuit overhead for the test features as well as test times and results.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"35 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Array architecture for ATG with 100% fault coverage\",\"authors\":\"K. El-Ayat, R. Cahn, C. L. Chan, T. Speers\",\"doi\":\"10.1109/DFTVS.1991.199966\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design implemented in the array circuit. In addition to architecture and circuit implementation details, the paper discusses the ATG generation methodology and algorithms, circuit overhead for the test features as well as test times and results.<<ETX>>\",\"PeriodicalId\":440536,\"journal\":{\"name\":\"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems\",\"volume\":\"35 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1991.199966\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1991.199966","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 15

摘要

讨论了一种用于自动生成测试向量的阵列结构、电路和方法。该架构已在基于反熔断的FPGA掩码编程版本中实现。该架构提供了电路中每个节点100%的可控性和可观察性。这允许自动生成具有100%故障覆盖率的测试向量，与阵列电路中实现的设计无关。除了架构和电路实现细节外，本文还讨论了ATG的生成方法和算法，测试功能的电路开销以及测试时间和结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Array architecture for ATG with 100% fault coverage

Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design implemented in the array circuit. In addition to architecture and circuit implementation details, the paper discusses the ATG generation methodology and algorithms, circuit overhead for the test features as well as test times and results.<>

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来源期刊

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems

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