基于28纳米CMOS技术的联想存储器LVDS驱动器和接收器设计

2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST) Pub Date : 2017-05-04 DOI:10.1109/MOCAST.2017.7937618

G. Traversi, F. Canio, V. Liberali, A. Stabile

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引用次数: 7

摘要

本文设计了一种用于新一代联想存储器(AM)芯片的LVDS输入/输出接口电路。联想记忆的带宽是一个需要解决的关键方面，以便增加每秒的比较次数。我们的目标是在500兆赫传输并行总线。由于大量接收器/驱动器将包含在AM芯片中，因此电路的功耗已被考虑在内。这项工作中讨论的设计已于2016年12月在28纳米CMOS技术上提交制造。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories

This paper presents the design of a LVDS input/output interface circuit for the next generation of Associative Memory (AM) chip. The bandwidth of Associative Memories is a critical aspect that needs to be addressed in order to increase the number of comparisons per second. Our aim is to transfer parallel buses at 500 MHz. Since a large number of receivers/drivers will be included in the AM chip, power consumption of the circuits has been taken into account. The design discussed in this work has been submitted for fabrication in December 2016 in a 28 nm CMOS technology.

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2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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