{"title":"在IP验证中导致受控随机化的方法/方法","authors":"Meghashyam Ashwathanarayan, G. Jayakrishna","doi":"10.1109/DTIS.2017.7930165","DOIUrl":null,"url":null,"abstract":"Post-silicon validation is the last level of inspecting the silicon before it is delivered to the customer. Automotive microcontrollers use Direct Memory Access (DMA) extensively in safety critical applications. This article explains how post-silicon validation can be improved to address the needs of the growing complexity of microcontrollers with a large number of Intellectual Property (IP). With increasing design complexity, aggressive scaling, and decreasing time to market, it is imperative to test the robustness of the microcontroller. Traditional test cases follow directed approach to testing and do not guarantee complete functional coverage. The proposed methodology uses the concept of constraint based randomization that is used in pre-silicon verification. The main advantage of using constraint based randomization in post-silicon validation is that millions of seeds can be executed in a very short time. This also stresses the silicon, increasing the likelihood of uncovering a bug which would not have been humanly possible to uncover at the pre-silicon stage.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A method/approach leading to controlled randomization in validation of an IP\",\"authors\":\"Meghashyam Ashwathanarayan, G. Jayakrishna\",\"doi\":\"10.1109/DTIS.2017.7930165\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Post-silicon validation is the last level of inspecting the silicon before it is delivered to the customer. Automotive microcontrollers use Direct Memory Access (DMA) extensively in safety critical applications. This article explains how post-silicon validation can be improved to address the needs of the growing complexity of microcontrollers with a large number of Intellectual Property (IP). With increasing design complexity, aggressive scaling, and decreasing time to market, it is imperative to test the robustness of the microcontroller. Traditional test cases follow directed approach to testing and do not guarantee complete functional coverage. The proposed methodology uses the concept of constraint based randomization that is used in pre-silicon verification. The main advantage of using constraint based randomization in post-silicon validation is that millions of seeds can be executed in a very short time. This also stresses the silicon, increasing the likelihood of uncovering a bug which would not have been humanly possible to uncover at the pre-silicon stage.\",\"PeriodicalId\":328905,\"journal\":{\"name\":\"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2017.7930165\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2017.7930165","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A method/approach leading to controlled randomization in validation of an IP
Post-silicon validation is the last level of inspecting the silicon before it is delivered to the customer. Automotive microcontrollers use Direct Memory Access (DMA) extensively in safety critical applications. This article explains how post-silicon validation can be improved to address the needs of the growing complexity of microcontrollers with a large number of Intellectual Property (IP). With increasing design complexity, aggressive scaling, and decreasing time to market, it is imperative to test the robustness of the microcontroller. Traditional test cases follow directed approach to testing and do not guarantee complete functional coverage. The proposed methodology uses the concept of constraint based randomization that is used in pre-silicon verification. The main advantage of using constraint based randomization in post-silicon validation is that millions of seeds can be executed in a very short time. This also stresses the silicon, increasing the likelihood of uncovering a bug which would not have been humanly possible to uncover at the pre-silicon stage.