Seungwook Lee, Seungwon Cha, D. Jang, Mihye Kim, Haewon Lee, Nakyung Lee, Seonok Kim, K. Oh, Daehyung Lee, Seung Ho Hong, H. Lee, Sung-Hun Oh, D. Park, Yitae Kim, JungChak Ahn
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A Low-Voltage 0.7 µm Pixel with 6000 e- Full-Well Capacity for a Low-Power CMOS Image Sensor
A low-voltage pixel with 0.7 µm pitch was designed for a low-power CMOS image sensor. By reducing a pixel power supply voltage (Vpix), power consumption for pixel was reduced, but full-well capacity (FWC) was also decreased. However, by lowering the conversion gain
(CG) and applying a negative voltage to the ground (NGND) of the pixel, FWC of 6000 e- was achieved without any degradation of both charge transfer lags and backflow noise. In addition, the signal linearity in the reduced analog-to-digital (ADC) range was improved by optimizing
the source follower (SF). For dark performances, white spots and dark current worsened by NGND were significantly improved by forcing more negative voltage to the transfer gate (TG) when it was turned off.
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