{"title":"坦佩雷理工大学的ASIC教育","authors":"H. Tenhunen, T. Korpiharju","doi":"10.1109/ASIC.1990.186158","DOIUrl":null,"url":null,"abstract":"The ASIC education program at the Tampere University of Technology is discussed. The design tools, educational activities, and foundry services are described. Hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level. Silicon foundry services through FINCHIP, NORCHIP, and EUROCHIP with field programmable gate array structures from Xilinx and Actel are utilized.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"ASIC education at Tampere University of Technology\",\"authors\":\"H. Tenhunen, T. Korpiharju\",\"doi\":\"10.1109/ASIC.1990.186158\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The ASIC education program at the Tampere University of Technology is discussed. The design tools, educational activities, and foundry services are described. Hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level. Silicon foundry services through FINCHIP, NORCHIP, and EUROCHIP with field programmable gate array structures from Xilinx and Actel are utilized.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"75 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186158\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186158","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
ASIC education at Tampere University of Technology
The ASIC education program at the Tampere University of Technology is discussed. The design tools, educational activities, and foundry services are described. Hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level. Silicon foundry services through FINCHIP, NORCHIP, and EUROCHIP with field programmable gate array structures from Xilinx and Actel are utilized.<>