通过资源按需(PARD)的可编程体系结构支持计算机中的差异化服务

Jiuyue Ma, Xiufeng Sui, Ninghui Sun, Yupeng Li, Zihao Yu, Bowen Huang, Tianni Xu, Zhicheng Yao, Yun Chen, Haibin Wang, Lixin Zhang, Yungang Bao
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引用次数: 39

摘要

本文介绍了PARD,一种用于按需资源的可编程体系结构,它提供了一种新的编程接口来将应用程序的高级信息(如服务质量需求)传递给硬件。PARD支持新的功能,比如完全由硬件支持的虚拟化和计算机中的差异化服务。PARD的灵感来自于这样一种观察:计算机本质上是一个网络,其中硬件组件通过数据包进行通信(例如,通过NoC或PCIe)。我们将软件定义网络的原则应用于这个计算机内部网络,并解决了三个主要挑战。首先,为了处理高级应用程序和底层硬件数据包之间的语义差距,PARD为每个内存访问、I/O或中断数据包附加了一个高级语义标签(例如,虚拟机或线程ID)。其次,为了使硬件组件更易于管理,PARD实现了可编程控制平面,这些控制平面可以集成到各种共享资源中(例如,缓存、DRAM和I/O设备),并且可以根据基于标签的规则对数据包进行不同的处理。第三,为了方便编程,PARD将所有控制平面抽象为一个设备文件树,以提供一个统一的编程接口,用户可以通过该接口创建和应用基于标记的规则。全系统仿真结果表明,通过将延迟关键型memcached应用程序与其他工作负载共存,PARD可以在不显著增加尾部延迟的情况下将四核计算机的CPU利用率提高至多四倍。基于初步RTL实现的FPGA仿真表明,缓存控制平面不会引入额外的延迟,并且内存控制平面可以将高优先级内存访问请求的排队延迟减少5.6倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Demand (PARD)
This paper presents PARD, a programmable architecture for resourcing-on-demand that provides a new programming interface to convey an application's high-level information like quality-of-service requirements to the hardware. PARD enables new functionalities like fully hardware-supported virtualization and differentiated services in computers. PARD is inspired by the observation that a computer is inherently a network in which hardware components communicate via packets (e.g., over the NoC or PCIe). We apply principles of software-defined networking to this intra-computer network and address three major challenges. First, to deal with the semantic gap between high-level applications and underlying hardware packets, PARD attaches a high-level semantic tag (e.g., a virtual machine or thread ID) to each memory-access, I/O, or interrupt packet. Second, to make hardware components more manageable, PARD implements programmable control planes that can be integrated into various shared resources (e.g., cache, DRAM, and I/O devices) and can differentially process packets according to tag-based rules. Third, to facilitate programming, PARD abstracts all control planes as a device file tree to provide a uniform programming interface via which users create and apply tag-based rules. Full-system simulation results show that by co-locating latencycritical memcached applications with other workloads PARD can improve a four-core computer's CPU utilization by up to a factor of four without significantly increasing tail latency. FPGA emulation based on a preliminary RTL implementation demonstrates that the cache control plane introduces no extra latency and that the memory control plane can reduce queueing delay for high-priority memory-access requests by up to a factor of 5.6.
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