基于多核加速器的异构嵌入式soc内存共享性能评估

Pirmin Vogel, A. Marongiu, L. Benini
{"title":"基于多核加速器的异构嵌入式soc内存共享性能评估","authors":"Pirmin Vogel, A. Marongiu, L. Benini","doi":"10.1145/2723772.2723775","DOIUrl":null,"url":null,"abstract":"Today's systems-on-chip (SoCs) more and more conform to the models envisioned by the Heterogeneous System Architecture (HSA) foundation in which massively parallel, programmable many-core accelerators (PMCAs) not only cooperate but also coherently share memory with a powerful, multi-core host processor. Allowing direct access to system memory from both sides greatly simplifies application development, but it increases the potential interference to the memory system due to the PMCA. In this work, we evaluate the impact of a PMCA's memory traffic on the host performance using the Xilinx Zynq-7000 SoC. This platform features a dual-core ARM Cortex-A9 CPU, as well as a field-programmable gate array (FPGA), which we use to model a PMCA. Synthetic workload, real benchmarks from the MiBench and ALPBench suites, and collaborative workloads all show that the interference generated by the PMCA can significantly reduce the memory bandwidth seen by the host (on average up to 25 % for host applications).","PeriodicalId":350480,"journal":{"name":"Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores","volume":"344 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"An Evaluation of Memory Sharing Performance for Heterogeneous Embedded SoCs with Many-Core Accelerators\",\"authors\":\"Pirmin Vogel, A. Marongiu, L. Benini\",\"doi\":\"10.1145/2723772.2723775\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Today's systems-on-chip (SoCs) more and more conform to the models envisioned by the Heterogeneous System Architecture (HSA) foundation in which massively parallel, programmable many-core accelerators (PMCAs) not only cooperate but also coherently share memory with a powerful, multi-core host processor. Allowing direct access to system memory from both sides greatly simplifies application development, but it increases the potential interference to the memory system due to the PMCA. In this work, we evaluate the impact of a PMCA's memory traffic on the host performance using the Xilinx Zynq-7000 SoC. This platform features a dual-core ARM Cortex-A9 CPU, as well as a field-programmable gate array (FPGA), which we use to model a PMCA. Synthetic workload, real benchmarks from the MiBench and ALPBench suites, and collaborative workloads all show that the interference generated by the PMCA can significantly reduce the memory bandwidth seen by the host (on average up to 25 % for host applications).\",\"PeriodicalId\":350480,\"journal\":{\"name\":\"Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores\",\"volume\":\"344 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-02-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/2723772.2723775\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2723772.2723775","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

摘要

当今的片上系统(soc)越来越符合异构系统架构(HSA)基础所设想的模型,在这种模型中,大规模并行、可编程的多核加速器(PMCAs)不仅可以协同工作,还可以与功能强大的多核主机处理器同步共享内存。允许从双方直接访问系统内存大大简化了应用程序开发,但是由于PMCA,它增加了对内存系统的潜在干扰。在这项工作中,我们使用Xilinx Zynq-7000 SoC评估PMCA内存流量对主机性能的影响。该平台采用双核ARM Cortex-A9 CPU,以及现场可编程门阵列(FPGA),我们使用它来建模PMCA。合成工作负载、来自MiBench和ALPBench套件的实际基准测试以及协作工作负载都表明,PMCA产生的干扰可以显着降低主机看到的内存带宽(对于主机应用程序平均高达25%)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Evaluation of Memory Sharing Performance for Heterogeneous Embedded SoCs with Many-Core Accelerators
Today's systems-on-chip (SoCs) more and more conform to the models envisioned by the Heterogeneous System Architecture (HSA) foundation in which massively parallel, programmable many-core accelerators (PMCAs) not only cooperate but also coherently share memory with a powerful, multi-core host processor. Allowing direct access to system memory from both sides greatly simplifies application development, but it increases the potential interference to the memory system due to the PMCA. In this work, we evaluate the impact of a PMCA's memory traffic on the host performance using the Xilinx Zynq-7000 SoC. This platform features a dual-core ARM Cortex-A9 CPU, as well as a field-programmable gate array (FPGA), which we use to model a PMCA. Synthetic workload, real benchmarks from the MiBench and ALPBench suites, and collaborative workloads all show that the interference generated by the PMCA can significantly reduce the memory bandwidth seen by the host (on average up to 25 % for host applications).
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