Y. Hristov, Simeon Dimitrov Kostadinov, D. Gaydazhiev, I. Uzunov
{"title":"采用32nm CMOS技术设计的电流模放大器的布局寄生效应对其性能的影响","authors":"Y. Hristov, Simeon Dimitrov Kostadinov, D. Gaydazhiev, I. Uzunov","doi":"10.1109/ET.2018.8549671","DOIUrl":null,"url":null,"abstract":"This paper investigates the influence of layout parasitic RC elements on the main parameters of a current mode amplifier designed in deep sub-micron CMOS technology - 32nm bulk CMOS process. Three distinct layout designs of the same amplifier circuit are implemented and compared by re-simulation. The effect of parasitic elements is investigated and estimated in the most appropriate layout. The statistical distribution of the main amplifier parameters due to process variation is received by Monte Carlo analysis.","PeriodicalId":374877,"journal":{"name":"2018 IEEE XXVII International Scientific Conference Electronics - ET","volume":"95 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Influence of the Layout Parasitic Effects on the Performance of Current Mode Amplifier Designed Using 32nm CMOS Technology\",\"authors\":\"Y. Hristov, Simeon Dimitrov Kostadinov, D. Gaydazhiev, I. Uzunov\",\"doi\":\"10.1109/ET.2018.8549671\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper investigates the influence of layout parasitic RC elements on the main parameters of a current mode amplifier designed in deep sub-micron CMOS technology - 32nm bulk CMOS process. Three distinct layout designs of the same amplifier circuit are implemented and compared by re-simulation. The effect of parasitic elements is investigated and estimated in the most appropriate layout. The statistical distribution of the main amplifier parameters due to process variation is received by Monte Carlo analysis.\",\"PeriodicalId\":374877,\"journal\":{\"name\":\"2018 IEEE XXVII International Scientific Conference Electronics - ET\",\"volume\":\"95 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE XXVII International Scientific Conference Electronics - ET\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ET.2018.8549671\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE XXVII International Scientific Conference Electronics - ET","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ET.2018.8549671","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Influence of the Layout Parasitic Effects on the Performance of Current Mode Amplifier Designed Using 32nm CMOS Technology
This paper investigates the influence of layout parasitic RC elements on the main parameters of a current mode amplifier designed in deep sub-micron CMOS technology - 32nm bulk CMOS process. Three distinct layout designs of the same amplifier circuit are implemented and compared by re-simulation. The effect of parasitic elements is investigated and estimated in the most appropriate layout. The statistical distribution of the main amplifier parameters due to process variation is received by Monte Carlo analysis.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
