{"title":"通过一种新颖的过孔优先、多硬掩膜工艺，用于亚100nm节点asic的低k SiOCH薄膜的容错铜双砷互连","authors":"H. Ohtake, M. Tagami, K. Arita, Y. Hayashi","doi":"10.1109/IEDM.2003.1269413","DOIUrl":null,"url":null,"abstract":"Misalignment-tolerant, Cu dual damascene interconnects (DDI) are successfully obtained in low-k SiOCH film (k=2.9) by a novel via-first multi-hard-mask (VF-MHM) process without via-poisoning of the photo-resist. In the VF-MHM, the etching sequence has higher misalignment margin between the vias and the upper lines in the Cu DDI as compared with a conventional trench-first one (TF-MHM). The VF-MHM process improves the fabrication yield and TDDB reliability of low-k/Cu-DDIs, and is a key scheme for sub-100 nm-node, ASIC fabrication.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Misalignment-tolerated, Cu dual damascene interconnects with low-k SiOCH film by a novel via-first, multi-hard-mask process for sub-100nm-node, ASICs\",\"authors\":\"H. Ohtake, M. Tagami, K. Arita, Y. Hayashi\",\"doi\":\"10.1109/IEDM.2003.1269413\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Misalignment-tolerant, Cu dual damascene interconnects (DDI) are successfully obtained in low-k SiOCH film (k=2.9) by a novel via-first multi-hard-mask (VF-MHM) process without via-poisoning of the photo-resist. In the VF-MHM, the etching sequence has higher misalignment margin between the vias and the upper lines in the Cu DDI as compared with a conventional trench-first one (TF-MHM). The VF-MHM process improves the fabrication yield and TDDB reliability of low-k/Cu-DDIs, and is a key scheme for sub-100 nm-node, ASIC fabrication.\",\"PeriodicalId\":344286,\"journal\":{\"name\":\"IEEE International Electron Devices Meeting 2003\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Electron Devices Meeting 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2003.1269413\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269413","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
摘要
在低k SiOCH薄膜(k=2.9)中，通过一种新型的先过孔多硬掩膜(VF-MHM)工艺，成功地获得了Cu双damascene互连(DDI)，并且没有光致抗蚀剂的过孔中毒。在VF-MHM中，与传统的沟槽优先蚀刻(TF-MHM)相比，在Cu DDI中过孔和上线之间的蚀刻顺序具有更高的偏差裕度。VF-MHM工艺提高了低k/ cu - ddi的成品率和TDDB可靠性，是100纳米以下节点ASIC制造的关键方案。
Misalignment-tolerated, Cu dual damascene interconnects with low-k SiOCH film by a novel via-first, multi-hard-mask process for sub-100nm-node, ASICs
Misalignment-tolerant, Cu dual damascene interconnects (DDI) are successfully obtained in low-k SiOCH film (k=2.9) by a novel via-first multi-hard-mask (VF-MHM) process without via-poisoning of the photo-resist. In the VF-MHM, the etching sequence has higher misalignment margin between the vias and the upper lines in the Cu DDI as compared with a conventional trench-first one (TF-MHM). The VF-MHM process improves the fabrication yield and TDDB reliability of low-k/Cu-DDIs, and is a key scheme for sub-100 nm-node, ASIC fabrication.
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