Opportunities and Challenges of Emerging Nanotechnologies for Future High-Speed and Low-Power Logic Applications

This presentation will highlight the opportunities and challenges ofnon-Si materials such as i) carbon-nanotubes (CNTs), ii) semiconductor-nanowires, iii) Ge, and iv) Ill-V materials for future high-speed, low-power logic applications. These materials, in general, have significantly higher intrinsic mobility (either hole or electron mobility) than Si, and they can potentially be used to replace Si as the channel material of the transistor to both enhance speed and reduce power. In this talk, emerging nanoelectronic devices such as semiconductor-nanowire field effect transistors (FETs) [1,2], carbon-nanotube FETs [1-3], Ge MOSFETs [4], strained Ge quantum-well FETs [4], and III-V compound semiconductor quantum-well FETs [4-6], are assessed for their potential in future high-performance, low-power computation applications. These emerging devices are benchmarked against state-of-the-art Si CMOS technologies in terms ofboth speed and power dissipation. The three fundamental transistor benchmarking metrics utilized in this study are i) intrinsic gate delay versus transistor physical gate length, ii) energy-delay product versus transistor physical gate length, and iii) intrinsic gate-delay versus the on-current/off-state leakage ratio (Ion/loff). While intrinsic device speed and switching energy are emphasized in the first and second metrics respectively, the tradeoff between device speed versus off-state leakage is assessed in the third metric. For high-speed and low-power logic applications, both low gate delay and low energy-delay product, as well as high Ion/loff ratios are required. The current status of these emerging nanoelectronic devices in light of the above metrics will be described in this talk. In addition, the merits and shortcomings, as well as the physics of operation of these devices, will be described. In addition to the above device aspects, the material and integration (onto silicon) aspects of these emerging nanotechnologies are significant as well. These non-Si materials will not replace Si, rather they will need to be integrated onto the silicon substrate. Both CNTs and semiconductor nanowires are formed using "bottom-up" chemical syntheses, and they currently suffer from the fundamental placement problem, i.e., there exists no practical nor reliable way to precisely align and position them. On the other hand, Ill-V and Ge materials can be patterned into desirable device structures using conventional "top-down" lithographic and etch techniques. In this regard, III-Vs and Ge are considered far more practical than CNTs and nanowires for future high-speed, low-power nanoelectronic device applications. In fact, Ill-V materials have been used in communication and optoelectronic products for quite some time. However, many significant challenges remain for III-V materials to become applicable for future high-speed, low-power logic applications. These include (i) finding a gate dielectric compatible with III-Vs, (ii) demonstrating transistor gate length scalability below 35 nm with acceptable Ion/loff ratio, (iii) improving the hole mobility in III-Vs or finding the right p-channel FET for the complementary metal-oxide-semiconductor (CMOS) configuration, and (iv) integrating Ill-V materials onto the Si substrate. While these are difficult challenges, much progress has been made recently [4,6]. If these problems can indeed be solved, III-Vs will play a major role in conjunction with silicon in future logic nanoelectronics. These challenges, along with potential solutions and recent progress, will be addressed in this presentation.