Pole-zero estimation and analysis of op-amp design with negative Miller compensation

In this paper, pole-zero estimation, analysis and simplification of the transfer function for a two-stage operational amplifier (op-amp) is presented. The circuit design considered is a folded cascode complementary metal oxide semiconductor (CMOS) op-amp incorporating both Miller and negative Miller frequency compensation. The design was created using a 0.35 µm CMOS fabrication process and analyzed for DC gain, unity gain frequency, gain margin, phase margin and open-loop pole and zero locations. Cadence Virtuoso was used for design entry and the Spectre simulator used for circuit level simulation studies. The extracted poles and zeros were used to create the circuit transfer function which was then analyzed using MATLAB. This allowed the transfer function to be simplified by reducing the numbers of poles and zeros for comparison with the frequency response of the original circuit. Finally, a Verilog-A model was created and compared to the original circuit and the MATLAB simulation study results.