A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down controller (SPDC) for reducing the standby current during power down, and locking range doubler for wide locking range. The digital DLL used for 3 Gbps 512 Mb GDDR3 SDRAM is fabricated using an 80 nm DRAM Process. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1.5 GHz operation frequency at 1.9 V, and a wide locking range from 50 MHz to 1.5 GHz.