{"title":"使用基于集中器的可增长交换机架构的160gb /s ATM交换机原型","authors":"K. Eng, M. Karol, G. Cyr, M.A. Pashan","doi":"10.1109/ICC.1995.525228","DOIUrl":null,"url":null,"abstract":"We describe the theory, design and implementation of a 2.5-Gb/s ATM switch growable to very large sizes, say 512/spl times/512 (1.28 Tb/s capacity), using a concentrator-based growable switch architecture. This architecture is based on a front-end concentrator-based cell distribution network followed by fixed-size ATM output switches. The front-end concentrator arrangement provides FIFO cell distribution with practical modularity and negligible cell loss. The ATM output switches are small-size shared memory designs that ensure optimal delay throughput performance for arbitrary traffic patterns. Our prototype consists of a complete and independent 2.5-Gb/s 8/spl times/8 ATM switch system with optical 2.4-Gb/s OC-48c and 155 Mb/s OC-3c interfaces, and also an expansion module (half shelf) capable of supporting eight such 8/spl times/8 switch systems yielding a total prototype capacity of 160 Gb/s.","PeriodicalId":241383,"journal":{"name":"Proceedings IEEE International Conference on Communications ICC '95","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A 160-Gb/s ATM switch prototype using the concentrator-based growable switch architecture\",\"authors\":\"K. Eng, M. Karol, G. Cyr, M.A. Pashan\",\"doi\":\"10.1109/ICC.1995.525228\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe the theory, design and implementation of a 2.5-Gb/s ATM switch growable to very large sizes, say 512/spl times/512 (1.28 Tb/s capacity), using a concentrator-based growable switch architecture. This architecture is based on a front-end concentrator-based cell distribution network followed by fixed-size ATM output switches. The front-end concentrator arrangement provides FIFO cell distribution with practical modularity and negligible cell loss. The ATM output switches are small-size shared memory designs that ensure optimal delay throughput performance for arbitrary traffic patterns. Our prototype consists of a complete and independent 2.5-Gb/s 8/spl times/8 ATM switch system with optical 2.4-Gb/s OC-48c and 155 Mb/s OC-3c interfaces, and also an expansion module (half shelf) capable of supporting eight such 8/spl times/8 switch systems yielding a total prototype capacity of 160 Gb/s.\",\"PeriodicalId\":241383,\"journal\":{\"name\":\"Proceedings IEEE International Conference on Communications ICC '95\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE International Conference on Communications ICC '95\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICC.1995.525228\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE International Conference on Communications ICC '95","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICC.1995.525228","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 160-Gb/s ATM switch prototype using the concentrator-based growable switch architecture
We describe the theory, design and implementation of a 2.5-Gb/s ATM switch growable to very large sizes, say 512/spl times/512 (1.28 Tb/s capacity), using a concentrator-based growable switch architecture. This architecture is based on a front-end concentrator-based cell distribution network followed by fixed-size ATM output switches. The front-end concentrator arrangement provides FIFO cell distribution with practical modularity and negligible cell loss. The ATM output switches are small-size shared memory designs that ensure optimal delay throughput performance for arbitrary traffic patterns. Our prototype consists of a complete and independent 2.5-Gb/s 8/spl times/8 ATM switch system with optical 2.4-Gb/s OC-48c and 155 Mb/s OC-3c interfaces, and also an expansion module (half shelf) capable of supporting eight such 8/spl times/8 switch systems yielding a total prototype capacity of 160 Gb/s.