Evaluation of a Filter-less AD-PLL with a Wide Input Frequency Range Using a Fast-Locking Algorithm

In this paper a Simulink model for a Filter-less All-digital Phase Locked Loop with a wide input frequency range and a fast-locking algorithm is presented. It was desirable to test the design's stability using different reference signals that covered a wide frequency range, specifically a 32.768kHz (RTC) reference and a 1MHz reference signal. The method for modeling and simulating the circuit is explained and then tested by observing the system's performance according to Simulink. The model was validated by comparing its lock time and jitter behavior against the Hspice design of the system for a 1MHz input reference. It was found that this filter-less AD-PLL system can be used at least with two of the most common crystal frequencies, RTC and 1MHz, which makes it highly compatible with IoT systems where a frequency synthesizer is required. The system locked onto the reference signal within 8 and 30 clock periods for a 1MHz reference, with an average of 19.2 clock periods, and within 6 and 48 clock periods for a RTC reference, with an average of 21.9 clock periods, across all configurations of the frequency divider in the feedback path, with jitter under 2.21% in all cases.