具有基于pla的可重构解码器的多功能存储单元

Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, S. Nakatake, Y. Takashima, Gong Chen
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引用次数: 0

摘要

特定于应用程序的内存使用是物联网设备嵌入式系统开发的重要关键。功能存储器单元,如内容可寻址存储器(CAM),对于特定于网络的应用程序来说是一个很好的解决方案。本工作提出一种新的功能记忆单元,可以重新配置记忆解码器的功能。在我们的可重构机制中,单开关单元被引入来扮演逻辑或电线的替代角色,并嵌入在SRAM存储器阵列中。一组单开关连接起来,构成一个可编程逻辑阵列(PLA)单元。与查找表(LUT)相比,PLA具有在小面积下实现多输入多输出功能的优势。因此,解码器的扩展功能由存储阵列内的PLA单元实现,PLA单元的组合提供了为存储数据配置各种功能的潜力,例如排序、过滤、纠错和加密/解密。在本文中,我们提出了一种基于PLA单元的功能存储单元的基本架构,并演示了使用PLA单元实现32位全加法器和2位计数器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A multi-functional memory unit with PLA-based reconfigurable decoder
An application-specific usage of memory is an important key in development of embedded systems for IoT devices. A functional memory unit such as content addressable memory (CAM) is a good solution for network-specific applications. This work proposes a novel functional memory unit which can reconfigure a function of the memory decoder. In our reconfigurable mechanism, uni-switch cells are introduced to play an alternative role of a logic or a wire, and are embedded in an SRAM memory array. A set of uni-switches is connected and constitutes a programmable logic array (PLA) unit. The PLA has a suitable advantage for a decoder that the multi-input and multi-output function can be realized with a small area, compared with look-up table (LUT). Hence, an extensional function of the decoder is realized by PLA units inside the memory array, and a combination of PLA units provides potentials to configure various functions for stored data such as sorting, filtering, error correction, and encryption/decryption. In this paper, we present a fundamental architecture of our functional memory unit with PLA units, and demonstrate an implementation of 32-bit full adder and 2-bit counter by using PLA units.
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