Tzu-Hsuan Hsu, Jau‐Ji Jou, Tien-Tsorng Shih, Y. Hung
{"title":"90纳米CMOS技术中光电二极管和跨阻放大器的单片集成","authors":"Tzu-Hsuan Hsu, Jau‐Ji Jou, Tien-Tsorng Shih, Y. Hung","doi":"10.1109/ICASI57738.2023.10179578","DOIUrl":null,"url":null,"abstract":"Herein, we designed and simulated the monolithic integration of photo-diode (PD) and transimpedance amplifier (TIA) in CMOS 90 nm technology. In the standard process, a PN-junction structure with an illuminated area of 39.48 $\\mu$m × 39.48 $\\mu$m was designed as the PD. The breakdown voltage of the PD is -10.5V. At a reverse bias voltage of 3V, the PD has a dark current of 2.6 pA and a capacitance of 1.03 pF. The TIA is composed of a regulated gate cascode circuit, a differential amplifier paralleling with an edge peak generator. The PD and the TIA are monolithically integrated, the overall transimpedance gain is 40.3 dB$\\Omega$, and the bandwidth is 4.1 GHz. The integrated design of PD and TIA could be applied in 5 Gb/s optical receivers.","PeriodicalId":281254,"journal":{"name":"2023 9th International Conference on Applied System Innovation (ICASI)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Monolithic Integration of Photo-Diode and Transimpedance Amplifier in CMOS 90 nm Technology\",\"authors\":\"Tzu-Hsuan Hsu, Jau‐Ji Jou, Tien-Tsorng Shih, Y. Hung\",\"doi\":\"10.1109/ICASI57738.2023.10179578\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Herein, we designed and simulated the monolithic integration of photo-diode (PD) and transimpedance amplifier (TIA) in CMOS 90 nm technology. In the standard process, a PN-junction structure with an illuminated area of 39.48 $\\\\mu$m × 39.48 $\\\\mu$m was designed as the PD. The breakdown voltage of the PD is -10.5V. At a reverse bias voltage of 3V, the PD has a dark current of 2.6 pA and a capacitance of 1.03 pF. The TIA is composed of a regulated gate cascode circuit, a differential amplifier paralleling with an edge peak generator. The PD and the TIA are monolithically integrated, the overall transimpedance gain is 40.3 dB$\\\\Omega$, and the bandwidth is 4.1 GHz. The integrated design of PD and TIA could be applied in 5 Gb/s optical receivers.\",\"PeriodicalId\":281254,\"journal\":{\"name\":\"2023 9th International Conference on Applied System Innovation (ICASI)\",\"volume\":\"189 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-04-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 9th International Conference on Applied System Innovation (ICASI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASI57738.2023.10179578\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 9th International Conference on Applied System Innovation (ICASI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASI57738.2023.10179578","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
在此，我们设计并模拟了光电二极管(PD)和跨阻放大器(TIA)在CMOS 90nm工艺下的单片集成。在标准工艺中，设计了一个照射面积为39.48 $\mu$ m × 39.48 $\mu$ m的pn结结构作为PD。PD击穿电压为-10.5V。在反向偏置电压为3V时，PD的暗电流为2.6 pA，电容为1.03 pF。TIA由一个稳压门级联电路、一个差分放大器和一个边峰发生器并联组成。PD和TIA采用单片集成，整体跨阻增益为40.3 dB $\Omega$，带宽为4.1 GHz。PD和TIA集成设计可以应用于5gb /s光接收机。
Monolithic Integration of Photo-Diode and Transimpedance Amplifier in CMOS 90 nm Technology
Herein, we designed and simulated the monolithic integration of photo-diode (PD) and transimpedance amplifier (TIA) in CMOS 90 nm technology. In the standard process, a PN-junction structure with an illuminated area of 39.48 $\mu$m × 39.48 $\mu$m was designed as the PD. The breakdown voltage of the PD is -10.5V. At a reverse bias voltage of 3V, the PD has a dark current of 2.6 pA and a capacitance of 1.03 pF. The TIA is composed of a regulated gate cascode circuit, a differential amplifier paralleling with an edge peak generator. The PD and the TIA are monolithically integrated, the overall transimpedance gain is 40.3 dB$\Omega$, and the bandwidth is 4.1 GHz. The integrated design of PD and TIA could be applied in 5 Gb/s optical receivers.
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