冯诺依曼瓶颈的光学喘息期

Optical Computing Pub Date : 1992-05-22 DOI:10.1364/optcomp.1991.tuc4

A. Dickinson

{"title":"冯诺依曼瓶颈的光学喘息期","authors":"A. Dickinson","doi":"10.1364/optcomp.1991.tuc4","DOIUrl":null,"url":null,"abstract":"The high end of microprocessor performance is currently dominated by Reduced Instruction Set Computer (RISC) architectures. These machines execute one or more instructions per clock cycle. A processor such as the i8601 [1] runs with a 40MHz clock - requiring that on average an instruction must be delivered to the CPU every 25nS. With DRAM access times currently at around 100nS, timely instruction delivery has become a critical constraint on processor speed.","PeriodicalId":302010,"journal":{"name":"Optical Computing","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An Optical Respite from the Von Neumann Bottleneck\",\"authors\":\"A. Dickinson\",\"doi\":\"10.1364/optcomp.1991.tuc4\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The high end of microprocessor performance is currently dominated by Reduced Instruction Set Computer (RISC) architectures. These machines execute one or more instructions per clock cycle. A processor such as the i8601 [1] runs with a 40MHz clock - requiring that on average an instruction must be delivered to the CPU every 25nS. With DRAM access times currently at around 100nS, timely instruction delivery has become a critical constraint on processor speed.\",\"PeriodicalId\":302010,\"journal\":{\"name\":\"Optical Computing\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Optical Computing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1364/optcomp.1991.tuc4\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Optical Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1364/optcomp.1991.tuc4","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

高端微处理器性能目前由精简指令集计算机(RISC)体系结构主导。这些机器每个时钟周期执行一条或多条指令。像i8601[1]这样的处理器以40MHz的时钟运行-要求平均每25nS必须向CPU传递一条指令。由于DRAM访问时间目前约为100nS，及时的指令传递已成为处理器速度的关键制约因素。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An Optical Respite from the Von Neumann Bottleneck

The high end of microprocessor performance is currently dominated by Reduced Instruction Set Computer (RISC) architectures. These machines execute one or more instructions per clock cycle. A processor such as the i8601 [1] runs with a 40MHz clock - requiring that on average an instruction must be delivered to the CPU every 25nS. With DRAM access times currently at around 100nS, timely instruction delivery has become a critical constraint on processor speed.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Optical Computing

自引率

0.00%

发文量