{"title":"用CMOS电路实现质心去模糊器模块","authors":"M. Mokarram, A. Khoei, K. Hadidi, K. Gheysari","doi":"10.1109/IS.2008.4670402","DOIUrl":null,"url":null,"abstract":"A voltage input current output multiplier and a current input voltage output divider circuit to realize the centre of gravity defuzzifier strategy is described in this paper. The proposed circuit has a compact architecture operating at higher speed and higher input voltage range compared to previously presented structures. The transistors operate in the both saturation and ohmic regions. The circuit operates with a single supply voltage of 3.3V in a 0.35 mum CMOS technology. The total harmonic distortion (THD) of multiplier is less than 1.1%, the linearity error is also less than 3%, and -3db frequency is more than 180 MHz with voltage input range of 3Vp-p. Simulation results are given to verify the functionality of the proposed circuits.","PeriodicalId":305750,"journal":{"name":"2008 4th International IEEE Conference Intelligent Systems","volume":"120 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Implementation of centroid defuzzifier block using CMOS circuits\",\"authors\":\"M. Mokarram, A. Khoei, K. Hadidi, K. Gheysari\",\"doi\":\"10.1109/IS.2008.4670402\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A voltage input current output multiplier and a current input voltage output divider circuit to realize the centre of gravity defuzzifier strategy is described in this paper. The proposed circuit has a compact architecture operating at higher speed and higher input voltage range compared to previously presented structures. The transistors operate in the both saturation and ohmic regions. The circuit operates with a single supply voltage of 3.3V in a 0.35 mum CMOS technology. The total harmonic distortion (THD) of multiplier is less than 1.1%, the linearity error is also less than 3%, and -3db frequency is more than 180 MHz with voltage input range of 3Vp-p. Simulation results are given to verify the functionality of the proposed circuits.\",\"PeriodicalId\":305750,\"journal\":{\"name\":\"2008 4th International IEEE Conference Intelligent Systems\",\"volume\":\"120 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 4th International IEEE Conference Intelligent Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IS.2008.4670402\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 4th International IEEE Conference Intelligent Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IS.2008.4670402","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
摘要
本文介绍了一种电压输入电流输出乘法器和电流输入电压输出分压器电路,以实现重心去模糊策略。与先前提出的结构相比,所提出的电路结构紧凑,运行速度更快,输入电压范围更大。晶体管工作在饱和区和欧姆区。该电路采用0.35 μ m CMOS技术,单电源电压为3.3V。乘频器的总谐波失真(THD)小于1.1%,线性误差小于3%,-3db频率大于180 MHz,电压输入范围为3Vp-p。仿真结果验证了所提电路的功能。
Implementation of centroid defuzzifier block using CMOS circuits
A voltage input current output multiplier and a current input voltage output divider circuit to realize the centre of gravity defuzzifier strategy is described in this paper. The proposed circuit has a compact architecture operating at higher speed and higher input voltage range compared to previously presented structures. The transistors operate in the both saturation and ohmic regions. The circuit operates with a single supply voltage of 3.3V in a 0.35 mum CMOS technology. The total harmonic distortion (THD) of multiplier is less than 1.1%, the linearity error is also less than 3%, and -3db frequency is more than 180 MHz with voltage input range of 3Vp-p. Simulation results are given to verify the functionality of the proposed circuits.