利用设计模块化和重新定位来提高基于fpga的计算系统的生产率

Zbigniew Mudza
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引用次数: 0

摘要

开发周期长是基于fpga的系统的一个重要缺点。为多个实例和跨不同设计重用模块的实现结果可以缓解这个问题。在具有严格设计约束的Xilinx 7系列设备中,可以强制对模块的多个实例进行相同的相对放置和路由。模块的参考实例可以在FPGA结构的某个部分中实现。可以从获得的结果中提取固定的放置和路由约束,并将其重新定位到FPGA结构的任何相同部分。这种方法在应用于可重构分区时特别有用——它支持可重构模块和静态设计的独立开发和实现。此外,在某些情况下,它可以扩展到重定位整个部分比特流。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Exploiting Design Modularity and Relocation to Increase Productivity in FPGA-based Computing Systems
Long development cycles are a crucial disadvantage of FPGA-based systems. Reusing implementation results of a module for multiple instances and across different designs can mitigate this issue. Identical relative placement and routing for multiple instances of a module can be forced in Xilinx 7 Series devices with strict design constraining. A reference instance of a module can be implemented in a certain section of FPGA fabric. Fixed placement and routing constraints can be extracted from the obtained results and relocated to any identical section of FPGA fabric. The approach is especially useful when applied to reconfigurable partitions – it supports independent development and implementation of reconfigurable modules and static design. Also, in some cases it can be extended to relocating entire partial bitstreams.
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