分段可寻址扫描架构

23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI:10.1109/VTS.2005.74

Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuck

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引用次数: 24

摘要

本文提出了一种解决数字集成电路测试中多种问题的测试体系结构。这些问题是测试数据量、测试应用时间、测试功耗和测试通道要求。在硬件开销最小的情况下，该体系结构至少为上述每个问题提供了一个数量级的减少。该架构依赖于扫描链分割和多热解码器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Segmented addressable scan architecture

This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.

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23rd IEEE VLSI Test Symposium (VTS'05)

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