生成树进位前瞻加法器的优化

Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers Pub Date : 1996-11-03 DOI:10.1109/ACSSC.1996.600852

J. Blackburn, L. Arndt, E. Swartzlander

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引用次数: 2

摘要

本文研究了64位生成树进位前置式加法器的优化问题，通过调整不同曼彻斯特进位链块中的晶体管尺寸和调整进位树内的块宽度来减少进位信号的临界延迟路径。使用HSPICE重新模拟了以前的生成树设计，参数为0.35 /spl mu/m CMOS工艺，与本文设计的电路进行了比较。在分析了使用16位进位选择边界的许多不同配置之后，设计并仿真了两个使用8位进位选择边界的电路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Optimization of spanning tree carry lookahead adders

This paper examines the optimization of the 64-bit spanning tree carry lookahead adder by sizing the transistors in the different Manchester carry chain blocks and by adjusting the block widths within the carry tree to reduce the critical delay paths of the carry signals. Previous spanning tree designs are re-simulated using HSPICE, with parameters for a 0.35 /spl mu/m CMOS process, to compare against the circuits designed for this paper. After analyzing many different configurations using the 16-bit carry select boundary, two circuits employing an 8-bit carry select boundary are designed and simulated.

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Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers

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