A stochastic heuristic based approach to test vector reordering for dynamic test power reduction

With the growth of IC technology, power minimization has become a serious concern for the test engineers. Power consumption in test mode is comparatively higher than in functional mode. This high power consumption during testing may generate too much heat which in turn can spoil the circuit under test. Considering the spectrum of low power testing approaches, reduction in dynamic power is viewed here as a sub-problem and resolved through test vector reordering. In this paper, an Enhanced Ant Colony Optimization (EACO) heuristic is applied to sort out an optimal order of test vectors so that switching activity during testing gets lessened. The simulation on ISCAS 85 bench mark test data set has shown promising power reduction when compared with simple ant colony optimization (ACO) and other relevant heuristic approaches.