Power Optimal Phase Locked Loop Using 90nm Technology with Five Stage CS-VCO

The design and analysis of the Phase Locked Loop (PLL) is suggested in this proposed paper. A feedback control system called a “Phase Locked Loop (PLL)” block automatically modifies a locally generated signals phase to match an input signals phase. PLL works by creating an oscillator frequency that matches the input signal frequency. The Phase Frequency Detector (PFD) in PLL is designed with 4 transistors anda charge pump (CP) is also designed with a reduction of only 4 transistors. To reduce the ripple, a loop filter is used, and a Current Starved five-stage voltage controller oscillator (CS-VCO)circuit with 22 transistors is used. Here Frequency Divider (FD) is designed with 9 transistors. The simulation is carried out in the GPDK90Nm technology. In this paper, the PLL and its block simulation results are provided. It is shown that a 1V D.C. supply delivers 22.63uW of power in a proposed PLL.