CMOS tapered buffer design for small width clock/data signal propagation

A new optimization criterion, the propagation of the minimum width pulse through the buffer is studied for design of tapered buffers draining capacitive loads. Contrary to the classic minimum delay criterion, this one produces buffers which support maximum speed signal propagation. Simulation results for a 0.8 /spl mu/m and a 0.35 /spl mu/m CMOS processes are analyzed. Semi-empirical relations are proposed to relate the minimum width pulse with the inverter gain ratio, the number of inverters, and the capacitive load. Additionally, a brief study of the delay skew of tapered buffers due to mismatching as a function of the gain ratio is done, showing that no severe degradation appears with small gain ratios. Finally, this work points out that buffers with small gain ratios should reach higher speeds, nearly 30% over the speed of buffers with gain ratio larger than a factor of 3.