{"title":"维特比算法的软件解决方案","authors":"M. Ikekawa, I. Kuroda","doi":"10.1109/VLSISP.1995.527480","DOIUrl":null,"url":null,"abstract":"Efficient software implementations of the Viterbi algorithm on two new generation processors, /spl mu/PD7701x and V830 are discussed. /spl mu/PD7701x is a 16-bit fixed point general purpose DSP which includes eight 40-bit general purpose registers, highly parallel operation capability, and conditional execution capability. V830 is a 32-bit RISC processor which has a multiply-accumulator and other special instructions for multimedia signal processing. These features enable effective implementations on both processors. The Viterbi decoders for rate 1/2 convolutional code are implemented on these processors and are two times faster than on conventional type DSPs.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Software solutions for the Viterbi algorithm\",\"authors\":\"M. Ikekawa, I. Kuroda\",\"doi\":\"10.1109/VLSISP.1995.527480\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Efficient software implementations of the Viterbi algorithm on two new generation processors, /spl mu/PD7701x and V830 are discussed. /spl mu/PD7701x is a 16-bit fixed point general purpose DSP which includes eight 40-bit general purpose registers, highly parallel operation capability, and conditional execution capability. V830 is a 32-bit RISC processor which has a multiply-accumulator and other special instructions for multimedia signal processing. These features enable effective implementations on both processors. The Viterbi decoders for rate 1/2 convolutional code are implemented on these processors and are two times faster than on conventional type DSPs.\",\"PeriodicalId\":286121,\"journal\":{\"name\":\"VLSI Signal Processing, VIII\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI Signal Processing, VIII\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSISP.1995.527480\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Signal Processing, VIII","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSISP.1995.527480","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficient software implementations of the Viterbi algorithm on two new generation processors, /spl mu/PD7701x and V830 are discussed. /spl mu/PD7701x is a 16-bit fixed point general purpose DSP which includes eight 40-bit general purpose registers, highly parallel operation capability, and conditional execution capability. V830 is a 32-bit RISC processor which has a multiply-accumulator and other special instructions for multimedia signal processing. These features enable effective implementations on both processors. The Viterbi decoders for rate 1/2 convolutional code are implemented on these processors and are two times faster than on conventional type DSPs.
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