Automatic generation of architectural models for designing dedicted VLIW signal processors

Some results of the CAPSYS method are presented. It is a new high-level synthesis method whose objective is to benefit from very long induction word (VLIW) compilation and digital signal processor (DSP) synthesis experiences to generalize the automatic processor design process. The major characteristic of this approach is to synthesize architecture in a global way. Instead of a single operative area, the synthesis considers a complete architecture. It permits one to take into account memory throughput, for instance, and, more generally, exchanges with the environment of the synthesized processor. The first part of the method, the generation of architectural models, is emphasized. This procedure furnishes a full spectrum of architectural decompositions (i.e. the number and the type of the functional units) from maximally parallel ones to fully serial ones. In each one, the synthesis algorithm creates an adequacy between the machine and the microcode. Results showing the influence of memory management on synthesized processors are given.<>