Error detection of arithmetic circuits using a residue checker with signed-digit number system

An error detection method for arithmetic circuits is proposed, by using a residue checker which consists of a number of residue arithmetic circuits designed based on radix-2 signed-digit (SD) number arithmetic. Fast modulo m(m=2/sup p//spl plusmn/1) multipliers and binary-to-residue number converters are constructed with a binary tree structure of modulo m SD adders. The modulo m addition is implemented by using a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. Therefore, the modulo m multiplication is performed in a time proportional to log/sub 2/p and an n-bit binary number is converted into a p-digit SD residue number in a time proportional to log/sub 2/(n/p). The presented residue arithmetic circuits can be applied to error detection for a large product-sum circuit.