{"title":"不可靠记忆中的进化算法","authors":"Haisoo Shin, Yun-Geun Lee, R. McKay, N. X. Hoai","doi":"10.1109/AHS.2009.24","DOIUrl":null,"url":null,"abstract":"Guaranteeing the underlying reliability of computer memory is becoming more difficult as chip dimensions scale down, and as power limitations make lower voltages desirable. To date, the reliability of memory has been seen as the responsibility of the computer engineer, any underlying unreliability being hidden from programmers. However it may make sense, in future, to shift this balance, optionally exposing the unreliability to programmers, permitting them to choose between higher and lower reliabilities. This is particularly relevant to the data-intensive applications which might potentially provide the \"killer apps\" for anticipated future many-core architectures. We simulated the effect of unreliable memory on the behaviour of a slightly re-programmed variant of a typical Genetic Algorithm (GA) on a range of optimisation problems. With only minor change to the code, most variables held in unreliable memory, and error rates up to 10^-3, the memory unreliability had no real effect on the GA behaviour. For higher error rates, the effects became noticeable, and the behaviour of the GA was unacceptable once the error rate reached 10^-2.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Evolutionary Algorithms in Unreliable Memory\",\"authors\":\"Haisoo Shin, Yun-Geun Lee, R. McKay, N. X. Hoai\",\"doi\":\"10.1109/AHS.2009.24\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Guaranteeing the underlying reliability of computer memory is becoming more difficult as chip dimensions scale down, and as power limitations make lower voltages desirable. To date, the reliability of memory has been seen as the responsibility of the computer engineer, any underlying unreliability being hidden from programmers. However it may make sense, in future, to shift this balance, optionally exposing the unreliability to programmers, permitting them to choose between higher and lower reliabilities. This is particularly relevant to the data-intensive applications which might potentially provide the \\\"killer apps\\\" for anticipated future many-core architectures. We simulated the effect of unreliable memory on the behaviour of a slightly re-programmed variant of a typical Genetic Algorithm (GA) on a range of optimisation problems. With only minor change to the code, most variables held in unreliable memory, and error rates up to 10^-3, the memory unreliability had no real effect on the GA behaviour. For higher error rates, the effects became noticeable, and the behaviour of the GA was unacceptable once the error rate reached 10^-2.\",\"PeriodicalId\":318989,\"journal\":{\"name\":\"2009 NASA/ESA Conference on Adaptive Hardware and Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 NASA/ESA Conference on Adaptive Hardware and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AHS.2009.24\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AHS.2009.24","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Guaranteeing the underlying reliability of computer memory is becoming more difficult as chip dimensions scale down, and as power limitations make lower voltages desirable. To date, the reliability of memory has been seen as the responsibility of the computer engineer, any underlying unreliability being hidden from programmers. However it may make sense, in future, to shift this balance, optionally exposing the unreliability to programmers, permitting them to choose between higher and lower reliabilities. This is particularly relevant to the data-intensive applications which might potentially provide the "killer apps" for anticipated future many-core architectures. We simulated the effect of unreliable memory on the behaviour of a slightly re-programmed variant of a typical Genetic Algorithm (GA) on a range of optimisation problems. With only minor change to the code, most variables held in unreliable memory, and error rates up to 10^-3, the memory unreliability had no real effect on the GA behaviour. For higher error rates, the effects became noticeable, and the behaviour of the GA was unacceptable once the error rate reached 10^-2.