Design and Analysis of 6T SRAM Implementation upon Dual Gate Junctionless FET

In this work, a Dual Gate Junction Less Field Effect Transistor (DGJLFET) with silicon channel length (Lc) and thickness (Tsi) of 20nm and 5nm respectively is proposed to implement Static Random Access Memory (SRAM) circuit for future memory applications. Dual Gate is designed to enhance the device gate control over the channel and to improve the current ratio. A junction-less device eliminates the problem of changing concentration gradient as source, drain, and channel regions have the same doping concentration and helps build smaller devices. The circuit implementation is carried out with the Look Up Table approach (LUT) which efficiently analyses circuits with nano-scaled devices. The performance demonstration of SRAM with the proposed DGJLFET in terms of stability in read, write and hold mode of operation is analyzed as 151mV, 263mV, and 406mV respectively.