R. Dhavse, Fyroos Muhammed, Chetna Sinha, V. Mishra, R. Patrikar
{"title":"以Si量子点作浮门的65nm FGMOS电容器的记忆特性","authors":"R. Dhavse, Fyroos Muhammed, Chetna Sinha, V. Mishra, R. Patrikar","doi":"10.1109/INDCON.2013.6725910","DOIUrl":null,"url":null,"abstract":"Tox scaling, which is otherwise saturated, is expected to get improved by the use of quantum dots in the floating gate layer of flash memory devices. Silicon quantum dots serve the task of multiple charge storage nodes and allow the use of ultra-thin tunnel oxides. Here, conventional Floating Gate Metal Oxide Semiconductor (FGMOS) gate stack capacitor is compared with similar structure where silicon nanocrystals are embedded in a thin oxide layer to behave like a floating gate. Their C-V curves exhibit similar memory effects. In this work, oxide thickness of 3.3 nm is used for target technology of 65 nm. Device threshold of 0.2 V is obtained with supply voltage of 1 V. The structures exhibit significant memory window with tunneling voltages as less as 12 V for a 65 nm device. All the simulations are performed using Sentaurus TCAD tools.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Memory characteristics of a 65 nm FGMOS capacitor with Si quantum dots as floating gates\",\"authors\":\"R. Dhavse, Fyroos Muhammed, Chetna Sinha, V. Mishra, R. Patrikar\",\"doi\":\"10.1109/INDCON.2013.6725910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Tox scaling, which is otherwise saturated, is expected to get improved by the use of quantum dots in the floating gate layer of flash memory devices. Silicon quantum dots serve the task of multiple charge storage nodes and allow the use of ultra-thin tunnel oxides. Here, conventional Floating Gate Metal Oxide Semiconductor (FGMOS) gate stack capacitor is compared with similar structure where silicon nanocrystals are embedded in a thin oxide layer to behave like a floating gate. Their C-V curves exhibit similar memory effects. In this work, oxide thickness of 3.3 nm is used for target technology of 65 nm. Device threshold of 0.2 V is obtained with supply voltage of 1 V. The structures exhibit significant memory window with tunneling voltages as less as 12 V for a 65 nm device. All the simulations are performed using Sentaurus TCAD tools.\",\"PeriodicalId\":313185,\"journal\":{\"name\":\"2013 Annual IEEE India Conference (INDICON)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 Annual IEEE India Conference (INDICON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/INDCON.2013.6725910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Annual IEEE India Conference (INDICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INDCON.2013.6725910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Memory characteristics of a 65 nm FGMOS capacitor with Si quantum dots as floating gates
Tox scaling, which is otherwise saturated, is expected to get improved by the use of quantum dots in the floating gate layer of flash memory devices. Silicon quantum dots serve the task of multiple charge storage nodes and allow the use of ultra-thin tunnel oxides. Here, conventional Floating Gate Metal Oxide Semiconductor (FGMOS) gate stack capacitor is compared with similar structure where silicon nanocrystals are embedded in a thin oxide layer to behave like a floating gate. Their C-V curves exhibit similar memory effects. In this work, oxide thickness of 3.3 nm is used for target technology of 65 nm. Device threshold of 0.2 V is obtained with supply voltage of 1 V. The structures exhibit significant memory window with tunneling voltages as less as 12 V for a 65 nm device. All the simulations are performed using Sentaurus TCAD tools.