On the Importance of Improving Cache Locality in Application-specific Accelerators via HLS

Designing an hardware architectiire using a lowlevel hardware description language (Verilog, VHDL) is a difficult and time-consuming task especially when the application is a complex and memory intensive one. A high-level synthesis (HLS) tool, most recently and actively being researched in several research groups, automatically generates an RTL description of the hardware architecture from a high-level (C/C++) program. However, application to be accelerated on the hardware via an HLS tool needs to be written in order to decrease the overall memory access latency by simply rewriting the code so that the reformatted loop structure will have more locality. In this paper, we present two case studies to decrease the memory access latency by improving the locality of a given application by reorganizing the memory access pattern of the application being accelerated via HLS on hardware that has a cache. We also emphasize the importance of locality in performance of hardware accelerators with our empirical results on a Zynq-based SoC platform.