M. Perrosé, P. Alba, M. Moulin, E. Augendre, J. Lugo, J. Raskin, S. Reboh
{"title":"离子非晶化和纳秒激光退火局部形成的多晶硅富阱层的射频优点图","authors":"M. Perrosé, P. Alba, M. Moulin, E. Augendre, J. Lugo, J. Raskin, S. Reboh","doi":"10.1109/SiRF56960.2023.10046145","DOIUrl":null,"url":null,"abstract":"We report on polysilicon trap-rich layers fabricated locally by ion implantation and nanosecond laser annealing on high-resistivity Si substrates. Using coplanar waveguides (of 1.5 mm length, $70 \\mu \\mathrm{m}$ central line width and $42 \\mu \\mathrm{m}$ spacing between central line and planar ground) we demonstrated RF figures of merit with the second harmonic of -84 dBm at an input RF power of 15 dBm and losses lower than 0.10 dB/mm at a 10 GHz frequency. The characteristics are stable with bias voltage. The proposed method is intended to fabricate trap-rich layers in selected wafer areas, potentially enabling the cointegration with FD-SOI technology.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"RF figures of merit of polysilicon trap-rich layers formed locally by ion amorphization and nanosecond laser annealing\",\"authors\":\"M. Perrosé, P. Alba, M. Moulin, E. Augendre, J. Lugo, J. Raskin, S. Reboh\",\"doi\":\"10.1109/SiRF56960.2023.10046145\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report on polysilicon trap-rich layers fabricated locally by ion implantation and nanosecond laser annealing on high-resistivity Si substrates. Using coplanar waveguides (of 1.5 mm length, $70 \\\\mu \\\\mathrm{m}$ central line width and $42 \\\\mu \\\\mathrm{m}$ spacing between central line and planar ground) we demonstrated RF figures of merit with the second harmonic of -84 dBm at an input RF power of 15 dBm and losses lower than 0.10 dB/mm at a 10 GHz frequency. The characteristics are stable with bias voltage. The proposed method is intended to fabricate trap-rich layers in selected wafer areas, potentially enabling the cointegration with FD-SOI technology.\",\"PeriodicalId\":354948,\"journal\":{\"name\":\"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-01-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SiRF56960.2023.10046145\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SiRF56960.2023.10046145","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
RF figures of merit of polysilicon trap-rich layers formed locally by ion amorphization and nanosecond laser annealing
We report on polysilicon trap-rich layers fabricated locally by ion implantation and nanosecond laser annealing on high-resistivity Si substrates. Using coplanar waveguides (of 1.5 mm length, $70 \mu \mathrm{m}$ central line width and $42 \mu \mathrm{m}$ spacing between central line and planar ground) we demonstrated RF figures of merit with the second harmonic of -84 dBm at an input RF power of 15 dBm and losses lower than 0.10 dB/mm at a 10 GHz frequency. The characteristics are stable with bias voltage. The proposed method is intended to fabricate trap-rich layers in selected wafer areas, potentially enabling the cointegration with FD-SOI technology.