{"title":"混合信号集成电路在电迁移和热载子效应下的灵敏度和可靠性评估","authors":"Xiangdong Xuan, A. Chatterjee","doi":"10.1109/DFTVS.2001.966785","DOIUrl":null,"url":null,"abstract":"With the use of aggressive technologies, the reliability of analog microelectronics is attracting greater attention. In this paper, a hierarchical reliability analysis approach for analog circuits is proposed. Through the use of behavioral models, electrical stress factors at the circuit inputs are propagated top-down to sub-modules and lower-level building-block components. These stress factors are then combined with physics-of-failure models to compute the performance degradation of the circuit building-block components due to electromigration and hot-carrier effects. The degradation effects are then propagated bottom-up through the design hierarchy to compute the changes in high-level circuit specification values due to electrical stress and the expected time-to-failure. A method for \"hot-spot\" analysis is proposed, where a \"hot-spot\" is defined to be a circuit component that can most likely cause circuit reliability problems. A reliability analysis tool has been developed and preliminary results are presented.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"Sensitivity and reliability evaluation for mixed-signal ICs under electromigration and hot-carrier effects\",\"authors\":\"Xiangdong Xuan, A. Chatterjee\",\"doi\":\"10.1109/DFTVS.2001.966785\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the use of aggressive technologies, the reliability of analog microelectronics is attracting greater attention. In this paper, a hierarchical reliability analysis approach for analog circuits is proposed. Through the use of behavioral models, electrical stress factors at the circuit inputs are propagated top-down to sub-modules and lower-level building-block components. These stress factors are then combined with physics-of-failure models to compute the performance degradation of the circuit building-block components due to electromigration and hot-carrier effects. The degradation effects are then propagated bottom-up through the design hierarchy to compute the changes in high-level circuit specification values due to electrical stress and the expected time-to-failure. A method for \\\"hot-spot\\\" analysis is proposed, where a \\\"hot-spot\\\" is defined to be a circuit component that can most likely cause circuit reliability problems. A reliability analysis tool has been developed and preliminary results are presented.\",\"PeriodicalId\":187031,\"journal\":{\"name\":\"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.2001.966785\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.2001.966785","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Sensitivity and reliability evaluation for mixed-signal ICs under electromigration and hot-carrier effects
With the use of aggressive technologies, the reliability of analog microelectronics is attracting greater attention. In this paper, a hierarchical reliability analysis approach for analog circuits is proposed. Through the use of behavioral models, electrical stress factors at the circuit inputs are propagated top-down to sub-modules and lower-level building-block components. These stress factors are then combined with physics-of-failure models to compute the performance degradation of the circuit building-block components due to electromigration and hot-carrier effects. The degradation effects are then propagated bottom-up through the design hierarchy to compute the changes in high-level circuit specification values due to electrical stress and the expected time-to-failure. A method for "hot-spot" analysis is proposed, where a "hot-spot" is defined to be a circuit component that can most likely cause circuit reliability problems. A reliability analysis tool has been developed and preliminary results are presented.