混合信号集成电路在电迁移和热载子效应下的灵敏度和可靠性评估

Xiangdong Xuan, A. Chatterjee
{"title":"混合信号集成电路在电迁移和热载子效应下的灵敏度和可靠性评估","authors":"Xiangdong Xuan, A. Chatterjee","doi":"10.1109/DFTVS.2001.966785","DOIUrl":null,"url":null,"abstract":"With the use of aggressive technologies, the reliability of analog microelectronics is attracting greater attention. In this paper, a hierarchical reliability analysis approach for analog circuits is proposed. Through the use of behavioral models, electrical stress factors at the circuit inputs are propagated top-down to sub-modules and lower-level building-block components. These stress factors are then combined with physics-of-failure models to compute the performance degradation of the circuit building-block components due to electromigration and hot-carrier effects. The degradation effects are then propagated bottom-up through the design hierarchy to compute the changes in high-level circuit specification values due to electrical stress and the expected time-to-failure. A method for \"hot-spot\" analysis is proposed, where a \"hot-spot\" is defined to be a circuit component that can most likely cause circuit reliability problems. A reliability analysis tool has been developed and preliminary results are presented.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"Sensitivity and reliability evaluation for mixed-signal ICs under electromigration and hot-carrier effects\",\"authors\":\"Xiangdong Xuan, A. Chatterjee\",\"doi\":\"10.1109/DFTVS.2001.966785\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the use of aggressive technologies, the reliability of analog microelectronics is attracting greater attention. In this paper, a hierarchical reliability analysis approach for analog circuits is proposed. Through the use of behavioral models, electrical stress factors at the circuit inputs are propagated top-down to sub-modules and lower-level building-block components. These stress factors are then combined with physics-of-failure models to compute the performance degradation of the circuit building-block components due to electromigration and hot-carrier effects. The degradation effects are then propagated bottom-up through the design hierarchy to compute the changes in high-level circuit specification values due to electrical stress and the expected time-to-failure. A method for \\\"hot-spot\\\" analysis is proposed, where a \\\"hot-spot\\\" is defined to be a circuit component that can most likely cause circuit reliability problems. A reliability analysis tool has been developed and preliminary results are presented.\",\"PeriodicalId\":187031,\"journal\":{\"name\":\"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.2001.966785\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.2001.966785","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18

摘要

随着先进技术的应用,模拟微电子的可靠性受到越来越多的关注。本文提出了一种模拟电路的分层可靠性分析方法。通过使用行为模型,电路输入端的电应力因子自上而下传播到子模块和较低级别的构建块组件。然后将这些应力因素与失效物理模型相结合,以计算由于电迁移和热载子效应导致的电路构建块组件的性能退化。然后,退化效应自下而上地通过设计层次结构传播,以计算由于电应力和预期故障前时间导致的高级电路规格值的变化。提出了一种“热点”分析方法,其中“热点”定义为最有可能导致电路可靠性问题的电路元件。开发了一种可靠性分析工具,并给出了初步结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Sensitivity and reliability evaluation for mixed-signal ICs under electromigration and hot-carrier effects
With the use of aggressive technologies, the reliability of analog microelectronics is attracting greater attention. In this paper, a hierarchical reliability analysis approach for analog circuits is proposed. Through the use of behavioral models, electrical stress factors at the circuit inputs are propagated top-down to sub-modules and lower-level building-block components. These stress factors are then combined with physics-of-failure models to compute the performance degradation of the circuit building-block components due to electromigration and hot-carrier effects. The degradation effects are then propagated bottom-up through the design hierarchy to compute the changes in high-level circuit specification values due to electrical stress and the expected time-to-failure. A method for "hot-spot" analysis is proposed, where a "hot-spot" is defined to be a circuit component that can most likely cause circuit reliability problems. A reliability analysis tool has been developed and preliminary results are presented.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信