多值逻辑神经网络的电流模CMOS实现

IEEE WESCANEX 93 Communications, Computers and Power in the Modern Environment - Conference Proceedings Pub Date : 1993-05-17 DOI:10.1109/WESCAN.1993.270575

M. Abd-El-Barr, R. Bolton, A.K. Jain

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引用次数: 2

摘要

提出了一种新的电路，用于在电流模CMOS逻辑(CMCL)技术中实现多值逻辑(MVL)神经元，这是一种近似于人类神经元的电子电路。给出了一组多值逻辑算子。这些操作符包括min、tsum、窗口文字、循环和补码。给出了实现mvl神经元的基本电路。本文还报道了HSPICE仿真结果，以验证MVL-neurode电路的运行。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Current-mode CMOS realization of a multiple-valued logic neurode

A new circuit is proposed for the realization of a multiple-valued logic (MVL) neurode, an electronic approximation of a human neuron, in a current-mode CMOS logic (CMCL) technology. A set of multiple-valued logic operators is presented. These operators include min, tsum, window literal, cycle, and complement. Basic circuits used to realize the MVL-neurode are also given. HSPICE simulation results to verify the operation of the MVL-neurode circuit are reported.<>

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IEEE WESCANEX 93 Communications, Computers and Power in the Modern Environment - Conference Proceedings

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