{"title":"B.C.D.乘数","authors":"M. B. Webster, P. W. Baker","doi":"10.1049/IJ-CDT.1979.0049","DOIUrl":null,"url":null,"abstract":"B.C.D. versions of known multiplier designs are presented; both achieve fast multiplication times without the high hardware cost typically associated with high speed. Serial b.c.d. addition and r.o.m. single-digit multipliers permit the substantial reductions in hardware cost, while higher clock frequencies offset the inherent slowness of the serial methods. Greatest cost-effectiveness is seen to be achieved through l.s.i. implementationn of a serial design which is easily extended for higher radix b.c.d. multiplication.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"B.C.D. multipliers\",\"authors\":\"M. B. Webster, P. W. Baker\",\"doi\":\"10.1049/IJ-CDT.1979.0049\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"B.C.D. versions of known multiplier designs are presented; both achieve fast multiplication times without the high hardware cost typically associated with high speed. Serial b.c.d. addition and r.o.m. single-digit multipliers permit the substantial reductions in hardware cost, while higher clock frequencies offset the inherent slowness of the serial methods. Greatest cost-effectiveness is seen to be achieved through l.s.i. implementationn of a serial design which is easily extended for higher radix b.c.d. multiplication.\",\"PeriodicalId\":344610,\"journal\":{\"name\":\"Iee Journal on Computers and Digital Techniques\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1979-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Iee Journal on Computers and Digital Techniques\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1049/IJ-CDT.1979.0049\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iee Journal on Computers and Digital Techniques","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/IJ-CDT.1979.0049","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
B.C.D. versions of known multiplier designs are presented; both achieve fast multiplication times without the high hardware cost typically associated with high speed. Serial b.c.d. addition and r.o.m. single-digit multipliers permit the substantial reductions in hardware cost, while higher clock frequencies offset the inherent slowness of the serial methods. Greatest cost-effectiveness is seen to be achieved through l.s.i. implementationn of a serial design which is easily extended for higher radix b.c.d. multiplication.
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