卷积编码器和维特比解码器的VHDL实现

Yin Sweet Wong, Wen Jian Ong, J. H. Chong, C. K. Ng, N. Noordin
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引用次数: 42

摘要

本文主要研究了利用现场可编程门阵列(FPGA)技术实现约束长度K为3、码率K /n为1/2的卷积编码器和自适应维特比解码器(AVD)。提出了一种具有不同回溯长度(TL)自适应解码能力的四态、基数为2的硬判决AVD。利用ISE 9.2和MATLAB仿真分析了实现的AVD的性能。AVD针对Xilinx xcv300r00q240 - 4 FPGA器件进行硬件实现。根据阈值信噪比(SNR)为6 dB的信道噪声特性变化,可以通过实现AVD重新配置译码器参数TL。综合结果表明,AVD实现的重构参数TL 4和15在FPGA器件利用率上有显著差异(>20%的提高)。结果还表明,与TL为15的模型相比,与TL为4的模型相比,重新配置的使用导致了28%的切片使用面积的改善,并且根据实时语音和视频的误码率(BER),解码精度的损失是可以容忍的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Implementation of convolutional encoder and Viterbi decoder using VHDL
This work focuses on the realization of convolutional encoder and adaptive Viterbi decoder (AVD) with a constraint length, K of 3 and a code rate (k/n) of 1/2 using field-programmable gate array (FPGA) technology. This paper presents a 4-state, radix-2, hard decision AVD which has the ability to decode adaptively through different traceback length (TL). The performance of the implemented AVD is analyzed by using ISE 9.2 and MATLAB simulations. The AVD is targeted to a Xilinx XCV300PQ240–4 FPGA device for hardware realization. The decoder parameter TL can be reconfigured via the implementation of AVD, in accordance with the changing channel noise characteristics of the threshold signal-to-noise ratio (SNR), which is 6 dB. The synthesis results show that the reconfiguration parameter TL of 4 and 15 of AVD implementation has significant difference (>20% improvement) in FPGA device utilization. The results also show that the use of reconfiguration leads to a 28% area occupancy of slice usage improvement over a TL of 15 model compared to a TL of 4 model with tolerable loss of decode accuracy, in accordance with the bit error rate (BER) for real-time voice and video.
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