{"title":"HDL逻辑合成中CPU控制器的优化","authors":"G. Yeap","doi":"10.1109/CICC.1997.606599","DOIUrl":null,"url":null,"abstract":"We present a procedure to optimize controllers of a CPU in a high-level description language (HDL) logic synthesis environment. The procedure is optimized for power and area efficiency of the controller. Applying the procedure on an actual controller of a RISC CPU, we realized up to 30% power as well as 20% area reduction compared to an unoptimized design. The procedure is applicable to any synthesizable HDL with symbolic state variables in its behavioral description.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"CPU controller optimization in HDL logic synthesis\",\"authors\":\"G. Yeap\",\"doi\":\"10.1109/CICC.1997.606599\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a procedure to optimize controllers of a CPU in a high-level description language (HDL) logic synthesis environment. The procedure is optimized for power and area efficiency of the controller. Applying the procedure on an actual controller of a RISC CPU, we realized up to 30% power as well as 20% area reduction compared to an unoptimized design. The procedure is applicable to any synthesizable HDL with symbolic state variables in its behavioral description.\",\"PeriodicalId\":111737,\"journal\":{\"name\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1997.606599\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606599","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CPU controller optimization in HDL logic synthesis
We present a procedure to optimize controllers of a CPU in a high-level description language (HDL) logic synthesis environment. The procedure is optimized for power and area efficiency of the controller. Applying the procedure on an actual controller of a RISC CPU, we realized up to 30% power as well as 20% area reduction compared to an unoptimized design. The procedure is applicable to any synthesizable HDL with symbolic state variables in its behavioral description.
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