基于FPGA的SAT组合等效检验加速器

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI:10.1109/IWSOC.2005.40

M. Safar, M. El-Kharashi, A. Salem

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引用次数: 1

摘要

本文提出了一种用于组合等效检验的软件/可重构硬件SAT加速器。将SAT二进制子句映射到蕴涵图中，将三元子句保存在索引子句数据库中，并将其映射到FPGA上实现的子句求值器和冲突检测器中。通过ISCAS’85基准电路验证了该方法的有效性。

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An FPGA based accelerator for SAT based combinational equivalence checking

In this paper we present software/reconfigurable hardware SAT accelerator for combinational equivalence checking. The SAT binary clauses are mapped into an implication graph and the ternary clauses are kept in an indexed clause database and mapped into the clause evaluator and conflict detector implemented on FPGA. The validity of the proposed approach is shown through the ISCAS'85 benchmark circuits.

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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

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