Minoru Inamori, K. Ishii, A. Tsutsui, K. Shirakawa, H. Nakada, T. Miyazaki
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A new processor architecture for digital signal transport systems
This paper proposes a new processor architecture for manipulating protocols in digital signal transport systems. To realize flexible and high-performance digital signal transport systems, the architecture has unique application-specific hardware with a core CPU. It is derived from an analysis of functions in real systems. A computer simulation confirms the efficiency of the architecture.