Extracting hierarchical description for VLSI circuits

Hierarchical modeling of VLSI circuits is important for many applications, viz. simulation, test generation, verification, etc. But unfortunately, the hierarchical knowledge associated with the circuit that the designer used, is lost or is not available at the time of test generation, simulation, and verification. The circuit is just viewed as an interconnection of gates and flip-flops. The circuit knowledge becomes unwieldy, and results in exponential search space for problems like test generation. This paper presents a simple scheme for extracting hierarchical descriptions for sequential circuits. The authors show an application to test generation. They model circuits using temporal logic.<>