Analysis of the substrate effect by the capacitive coupling in SOI UTBB Transistors

The goal of this work is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with the application of a selected set of back gate biases (VSUB) through DC and AC simulations. A set of different ground planes (GP) arrangements has been considered. It has been shown that the degradation due to the substrate effects increases as the substrate bias is reduced. According to the analysis, it could be observed the GP type influences the capacitive coupling of the structure as the back gate bias is varied. Additionally, it has been shown that the presence of the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the device.