{"title":"格子滤波器在TMS320C62xx上用ETSI数学运算实现","authors":"A. Buvaneswari, M. Haner","doi":"10.1109/ACSSC.2002.1196953","DOIUrl":null,"url":null,"abstract":"The specific lattice filter implementations considered here are the short-term analysis and synthesis filter realizations in the GSM Full Rate (06.10) specifications. With the ETSI math operations like multiply with round (mult-r) to be performed, and with TMS320C62xx's instruction set not consisting of any mult-r or even round operation, the C-compiler generated code fails to achieve the best performance. With techniques like unrolling the loop, intelligent scheduling of the math operations in the pipeline etc., and hand coding in assembly, we show how to achieve a performance better than that of a processor with operations like mult-r in its instruction set.","PeriodicalId":284950,"journal":{"name":"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Lattice filter implementation with ETSI math operations on the TMS320C62xx\",\"authors\":\"A. Buvaneswari, M. Haner\",\"doi\":\"10.1109/ACSSC.2002.1196953\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The specific lattice filter implementations considered here are the short-term analysis and synthesis filter realizations in the GSM Full Rate (06.10) specifications. With the ETSI math operations like multiply with round (mult-r) to be performed, and with TMS320C62xx's instruction set not consisting of any mult-r or even round operation, the C-compiler generated code fails to achieve the best performance. With techniques like unrolling the loop, intelligent scheduling of the math operations in the pipeline etc., and hand coding in assembly, we show how to achieve a performance better than that of a processor with operations like mult-r in its instruction set.\",\"PeriodicalId\":284950,\"journal\":{\"name\":\"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.2002.1196953\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.2002.1196953","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
这里考虑的具体晶格滤波器实现是GSM Full Rate(06.10)规范中的短期分析和合成滤波器实现。由于要执行ETSI数学运算,如乘与四舍五入(mult-r),而TMS320C62xx的指令集不包含任何mult-r甚至四舍五入操作,c编译器生成的代码无法达到最佳性能。通过展开循环、在流水线中智能调度数学运算等技术,以及汇编代码手工编码,我们展示了如何实现比指令集中具有multi -r等操作的处理器更好的性能。
Lattice filter implementation with ETSI math operations on the TMS320C62xx
The specific lattice filter implementations considered here are the short-term analysis and synthesis filter realizations in the GSM Full Rate (06.10) specifications. With the ETSI math operations like multiply with round (mult-r) to be performed, and with TMS320C62xx's instruction set not consisting of any mult-r or even round operation, the C-compiler generated code fails to achieve the best performance. With techniques like unrolling the loop, intelligent scheduling of the math operations in the pipeline etc., and hand coding in assembly, we show how to achieve a performance better than that of a processor with operations like mult-r in its instruction set.