Low noise amplifier linearization for near millimeter wave band applications

In this paper, an improved post linearization technique is presented for high frequency low noise amplifiers (LNAs). It employs two auxiliary diode-connected NMOS-PMOS transistors with a resistor and a capacitor which increases the linearity while partially compensates the gain reduction. This technique improves the IIP3 more than 7 dB by reducing the third-order nonlinearity coefficient of output current. The proposed method has been implemented on a two-stage LNA consisting of a common-source stage and a cascode stage. This LNA has been simulated in a 0.18μm RF CMOS technology consuming only 13.9 mW from a single 1.8-V power supply.