验证Promela/SPIN中MARTE/CCSL时间要求

2011 16th IEEE International Conference on Engineering of Complex Computer Systems Pub Date : 2011-04-27 DOI:10.1109/ICECCS.2011.14

Ling Yin, F. Mallet, Jing Liu

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引用次数: 39

摘要

时钟约束规范语言(Clock Constraint Specification Language, CCSL)提供了表达式和关系来指定系统的时间需求和因果依赖关系。它最初是在MARTE的背景下提出的:实时和嵌入式系统建模和分析的UML概要文件。在本文中，我们提出一种验证CCSL规范的方法。我们给出了CCSL时钟约束的一个基本子集的正式的基于状态的解释。在此基础上，我们将CCSL规范转换为Promela模型，并将结果提供给模型检查器SPIN。然后给出了模型属性的表达模式，并进行了验证。最后以一个数字滤波器应用为例说明了该方法。

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Verification of MARTE/CCSL Time Requirements in Promela/SPIN

The Clock Constraint Specification Language (CCSL) provides expressions and relations to specify the time requirements and causal dependencies of systems. It was initially proposed, in the context of MARTE: the UML profile for Modeling and Analysis of Real-Time and Embedded Systems. In this paper, we propose a method to verify CCSL specifications. We give a formal state-based interpretation of a fundamental subset of CCSL clock constraints. Based on it, we translate a CCSL specification into a Promela model and feed the result into the model checker SPIN. Then we show some patterns for expressing the properties of the model and do the verification. A digital filter application is used as an example to illustrate the approach.

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2011 16th IEEE International Conference on Engineering of Complex Computer Systems

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