{"title":"H.264/AVC熵编码器的低成本Exp_Golomb硬件架构","authors":"Ben Hamida Asma, Dhahri Salah, A. Zitouni","doi":"10.1109/ICM.2018.8704000","DOIUrl":null,"url":null,"abstract":"The Exponential Golomb and Context Adaptive Variable Length Coding are the entropy eoding tools for H.264/AVC in baseline proffle. Since the Exp_Golomb is based on variable length codes with a regular construction, strong error resilience is achieved. However, its hardware implementation causes a challenge due to the logarithmic operation. This paper presents a low-cost hardware architecture for Exp_Golomb. Furthermore, a \"shift number counting method\" is proposed to solve the key problem of logarithmic operation. This method can significantly simplify the hardware architecture and reduce the area cost. The proposed design has been synthesized with ISE Xilinx on Virtex IV and functionally verified by RTL simulations. The results show that the proposed design occupies 126 LUT slice and has a clock frequency about 250 MHz.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low-cost Exp_Golomb hardware architecture for H.264/AVC entropy coder\",\"authors\":\"Ben Hamida Asma, Dhahri Salah, A. Zitouni\",\"doi\":\"10.1109/ICM.2018.8704000\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Exponential Golomb and Context Adaptive Variable Length Coding are the entropy eoding tools for H.264/AVC in baseline proffle. Since the Exp_Golomb is based on variable length codes with a regular construction, strong error resilience is achieved. However, its hardware implementation causes a challenge due to the logarithmic operation. This paper presents a low-cost hardware architecture for Exp_Golomb. Furthermore, a \\\"shift number counting method\\\" is proposed to solve the key problem of logarithmic operation. This method can significantly simplify the hardware architecture and reduce the area cost. The proposed design has been synthesized with ISE Xilinx on Virtex IV and functionally verified by RTL simulations. The results show that the proposed design occupies 126 LUT slice and has a clock frequency about 250 MHz.\",\"PeriodicalId\":305356,\"journal\":{\"name\":\"2018 30th International Conference on Microelectronics (ICM)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 30th International Conference on Microelectronics (ICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2018.8704000\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 30th International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2018.8704000","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-cost Exp_Golomb hardware architecture for H.264/AVC entropy coder
The Exponential Golomb and Context Adaptive Variable Length Coding are the entropy eoding tools for H.264/AVC in baseline proffle. Since the Exp_Golomb is based on variable length codes with a regular construction, strong error resilience is achieved. However, its hardware implementation causes a challenge due to the logarithmic operation. This paper presents a low-cost hardware architecture for Exp_Golomb. Furthermore, a "shift number counting method" is proposed to solve the key problem of logarithmic operation. This method can significantly simplify the hardware architecture and reduce the area cost. The proposed design has been synthesized with ISE Xilinx on Virtex IV and functionally verified by RTL simulations. The results show that the proposed design occupies 126 LUT slice and has a clock frequency about 250 MHz.