Hiroki Mikami, K. Torigoe, Makoto Inokawa, M. Edahiro
{"title":"基于多核软硬件接口的LLVM指令延迟测量","authors":"Hiroki Mikami, K. Torigoe, Makoto Inokawa, M. Edahiro","doi":"10.24297/ijct.v22i.9231","DOIUrl":null,"url":null,"abstract":"The increasing scale and complexity of embedded systems and the use of multi-many-core processors have resulted in a corresponding increase in the demand for software development with a high degree of parallelism. The degree of parallelism in software and the accuracy of performance estimation in the early design stages of model-based development can be improved by estimating performance of blocks in models and utilizing the estimate for parallelization. Research is therefore being performed on a software performance estimation technique that uses the IEEE2804-2019 hardware feature description called software-hardware interface for multi-many-core (SHIM). In SHIM, each LLVM-IR instruction is associated with the execution cycle of the target processor. Because several types of assembly instruction sequences for the target processor are generated from a given LLVM-IR instruction, it is not easy to estimate the number of execution cycles. In this study, we propose a regression analysis method to estimate the execution cycles for each LLVM-IR instruction. It is observed that our method estimated the execution cycles within the target error of ±20% in experiments using a Raspberry Pi3 Model B+.","PeriodicalId":210853,"journal":{"name":"INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"LLVM Instruction Latency Measurement for Software-Hardware Interface for Multi-many-core\",\"authors\":\"Hiroki Mikami, K. Torigoe, Makoto Inokawa, M. Edahiro\",\"doi\":\"10.24297/ijct.v22i.9231\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The increasing scale and complexity of embedded systems and the use of multi-many-core processors have resulted in a corresponding increase in the demand for software development with a high degree of parallelism. The degree of parallelism in software and the accuracy of performance estimation in the early design stages of model-based development can be improved by estimating performance of blocks in models and utilizing the estimate for parallelization. Research is therefore being performed on a software performance estimation technique that uses the IEEE2804-2019 hardware feature description called software-hardware interface for multi-many-core (SHIM). In SHIM, each LLVM-IR instruction is associated with the execution cycle of the target processor. Because several types of assembly instruction sequences for the target processor are generated from a given LLVM-IR instruction, it is not easy to estimate the number of execution cycles. In this study, we propose a regression analysis method to estimate the execution cycles for each LLVM-IR instruction. It is observed that our method estimated the execution cycles within the target error of ±20% in experiments using a Raspberry Pi3 Model B+.\",\"PeriodicalId\":210853,\"journal\":{\"name\":\"INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.24297/ijct.v22i.9231\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.24297/ijct.v22i.9231","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
LLVM Instruction Latency Measurement for Software-Hardware Interface for Multi-many-core
The increasing scale and complexity of embedded systems and the use of multi-many-core processors have resulted in a corresponding increase in the demand for software development with a high degree of parallelism. The degree of parallelism in software and the accuracy of performance estimation in the early design stages of model-based development can be improved by estimating performance of blocks in models and utilizing the estimate for parallelization. Research is therefore being performed on a software performance estimation technique that uses the IEEE2804-2019 hardware feature description called software-hardware interface for multi-many-core (SHIM). In SHIM, each LLVM-IR instruction is associated with the execution cycle of the target processor. Because several types of assembly instruction sequences for the target processor are generated from a given LLVM-IR instruction, it is not easy to estimate the number of execution cycles. In this study, we propose a regression analysis method to estimate the execution cycles for each LLVM-IR instruction. It is observed that our method estimated the execution cycles within the target error of ±20% in experiments using a Raspberry Pi3 Model B+.