{"title":"先进ESM系统的多圆缓冲控制器芯片","authors":"F. Godon, D. Al-Khalili, R. Inkol","doi":"10.1109/ASIC.1990.186190","DOIUrl":null,"url":null,"abstract":"A 90 K transistor 1.5 mu m CMOS integrated circuit that operates at a data transfer rate of 20 MHz and implements an array of variable size circular buffers mapped into a high-speed RAM through physical and virtual addressing techniques is discussed. The device is fully programmable with the capability of single and block data transfers. The target application is an advanced multiprocessor ESM system.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Multi circular buffer controller chip for advanced ESM system\",\"authors\":\"F. Godon, D. Al-Khalili, R. Inkol\",\"doi\":\"10.1109/ASIC.1990.186190\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 90 K transistor 1.5 mu m CMOS integrated circuit that operates at a data transfer rate of 20 MHz and implements an array of variable size circular buffers mapped into a high-speed RAM through physical and virtual addressing techniques is discussed. The device is fully programmable with the capability of single and block data transfers. The target application is an advanced multiprocessor ESM system.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"71 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186190\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186190","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
讨论了一种90 K晶体管1.5 μ m CMOS集成电路,其数据传输速率为20 MHz,并通过物理和虚拟寻址技术实现了一系列可变大小的圆形缓冲区映射到高速RAM中。该设备是完全可编程的,具有单个和块数据传输的能力。目标应用程序是一个先进的多处理器ESM系统
Multi circular buffer controller chip for advanced ESM system
A 90 K transistor 1.5 mu m CMOS integrated circuit that operates at a data transfer rate of 20 MHz and implements an array of variable size circular buffers mapped into a high-speed RAM through physical and virtual addressing techniques is discussed. The device is fully programmable with the capability of single and block data transfers. The target application is an advanced multiprocessor ESM system.<>